Tohoku University and Aisin Develop a 16nm AI Chip With On-Chip STT-MRAM That Boots in 65.7 Milliseconds

Tohoku University and automotive parts maker Aisin announced on November 2 that they have developed an AI chip with built-in STT-MRAM, a type of non-volatile memory that keeps data when the power is off, MONOist reported on November 4. The partners say it is the world’s first 16nm AI system-on-chip to carry STT-MRAM. The work comes from a team led by Professor Tetsuo Endoh at the university’s Center for Innovative Integrated Electronic Systems, together with Aisin engineers.

The chip is made on TSMC’s 16nm FinFET process and combines 32MB of STT-MRAM with an AI accelerator, two Arm Cortex-A53 CPU cores and an Arm Mali-G31 GPU. It follows a near-memory computing design: the MRAM holds both the operating system’s boot data and the AI model weights next to the processors, so the chip needs no external DRAM or SSD. In a conventional setup, DRAM has to be initialised and the bootloader and model data copied from an SSD before anything runs. With the new design, the time from power-on to the OS kernel starting fell from 2,535.3 milliseconds to 65.7 milliseconds, about 38.59 times faster.

To fit models into the limited memory, the team built a hybrid multiplier that mixes 8-bit and 16-bit operations. Running the Tiny YOLOv3 image recognition model, this cut the weight data from 17.7MB to 9.36MB, a 53% reduction, while the detection accuracy score (mAP) slipped only from 0.325 to 0.316. Chip-level AI processing time dropped from 594.6 milliseconds to 58.5 milliseconds, the system as a whole ran about 25 times faster, and inference energy came to 50.7 millijoules per frame, roughly one fiftieth of the conventional approach.

What it means in practice

Tohoku University and Aisin Develop a 16nm AI Chip With On-Chip STT-MRAM That Boots in 65.7 Milliseconds — contextual photo

Fast start-up and low energy matter most in edge devices that are switched on and off often, such as vehicle systems, which is where a supplier like Aisin has an obvious interest. The result adds to a run of Japanese hardware work aimed at AI efficiency, from Hitachi’s GPU cold plate for AI data centres to Preferred Networks’ plans to mass-produce its MN-Core chips, although this chip targets small devices rather than servers.

The results are being presented at the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2026, held in Hsinchu, Taiwan, from November 1 to 4. The announcement gave no timeline for products, so what to watch is whether Aisin moves the design into automotive parts and how it performs with models larger than Tiny YOLOv3.